As integrated circuit art has advanced, more and more circuit devices, and consequently more circuits and circuit functions, have been placed on single chips. These circuits perform many different functions, and the circuits must be tested before they are put into use. Many circuits can be tested using external testers, i.e., testers which are not a part of or formed on the chip, but rather are separate stand-alone machines. Such circuits as memories in SIMMs or other add-on card or modules may be so tested. However, there are certain circuits that are not amenable to testing by such external machines for various reasons. For example, various memories associated with microprocessors do not have any external access pads or other means to connect to external machines for testing. A solution to this problem is to form test circuits directly on the same chip as the chip devices and other circuit components are formed. These embedded circuits are often referred to as a built-in self-test (BIST). A typical BIST is shown and described in U.S. Pat. No. 5,173,906 issued Dec. 22, 1992, and entitled "BUILT-IN SELF TEST FOR INTEGRATED CIRCUITS," which patent is hereby incorporated herein by reference. This BIST works very well and provides the necessary test functions to memories that are utilized in conjunction with or as a part of a microprocessor. However, with this on-chip tester, as with other BISTs, a separate BIST is required for each memory being tested or at least with each different type or size memory. While this can be done, each BIST requires a certain amount of space, or area on the surface of the chip, which space can be as much as 2-3% of the area of the chip with which it is associated and which it tests. A single BIST would be desirable to test all of the memories, and thus save valuable area on the chip surface. However, there are two major constraints to such a solution. First, no significant extra time should be needed for the testing, and such a BIST must be capable of performing all of the test functions and patterns required for each of the various memories irrespective of their sizes, types or characteristics.